View SX1223_1089274.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev 5 may 2007 www.semtech.com SX1223 SX1223 425 C 475 mhz / 850 C 950 mhz integrated uhf transmitter general description the SX1223 is a single chip transmitter operating in uhf frequency bands including the 434, 869 and 915 mhz license-free ism (industrial scientific and medical) bands. its highly integrated architecture allows for minimum external components while maintaining design flexibility. all major rf communication parameters are programmable and most of them can be set dynamically. the SX1223 offers the advantage of high data rate communication at rates of up to 153.6 kbit/s. the SX1223 is optimized for low cost applications while offering h igh rf output power. the device is suitable for applications which have to satisfy either the europe an (etsi-300-220) or the north american (fcc part 15) regulatory standards. applications automated meter reading (amr) home automation and access control high-quality speech, music and data over rf key product features rf output power: up to +10 dbm low power consumption: t x = 25.8 ma @ 10 dbm (typical) supply voltage down to 2.0 v data rate from 1.2 to 153.6 kbit/s on-chip frequency synthesizer continuous phase 2-level fsk modulation very small rohs green package (tqfn24, 4mm x 4mm) ordering information part number temperature range package SX1223i073trt (1) -40 c to +85 c tqfn24 (1) tr refers to tape & reel. t refers to lead free package. this device is weee and rohs compliant.
? semtech 2007 www.semtech.com 2 SX1223 table of contents 1 functional block diagram ........................... ................................................... .................................... 3 2 pin description.................................... ................................................... .............................................. 4 3 electrical characteristics......................... ................................................... ........................................ 5 3.1 absolute maximum operating ranges.................. ................................................... ............................. 5 3.2 specifications ..................................... ................................................... ................................................ 5 3.2.1 operating range .................................... ................................................... ............................................ 5 3.2.2 electrical specifications.......................... ................................................... ............................................ 5 4 general description................................ ................................................... .......................................... 7 4.1 frequency synthesizer.............................. ................................................... .......................................... 7 4.1.1 general structure .................................. ................................................... ............................................. 7 4.1.2 crystal oscillator ................................. ................................................... ............................................... 8 4.1.3 vco................................................ ................................................... ................................................... . 8 4.1.4 charge pump ........................................ ................................................... ........................................... 10 4.1.5 loop filter........................................ ................................................... ................................................. 10 4.1.6 lock detect........................................ ................................................... ............................................... 11 4.2 modulator.......................................... ................................................... ................................................ 11 4.2.1 introduction....................................... ................................................... ................................................ 11 4.2.2 data interface ..................................... ................................................... .............................................. 11 4.2.3 bit rate setting for mw1 and mw2 ................... ................................................... .............................. 12 4.2.4 deviation setting for mw1 and mw2 .................. ................................................... ............................. 12 4.2.5 shaping for mw1 and mw2 ............................ ................................................... ................................. 13 4.2.6 modulator saturation for mw1 and mw2............... ................................................... .......................... 13 4.2.7 summary of modulator settings for mw1 and mw2...... ................................................... .................. 13 4.2.8 frequency deviation setting for mw3................ ................................................... ............................... 13 4.3 power amplifier .................................... ................................................... ............................................ 14 4.4 voltage regulators ................................. ................................................... ........................................... 14 5 serial interface definition and principles of opera tion ............................................... ................... 15 5.1 serial control interface........................... ................................................... .......................................... 15 5.2 configuration and status registers ................. ................................................... .................................. 16 5.2.1 operating modes .................................... ................................................... .......................................... 16 5.2.2 other settings..................................... ................................................... .............................................. 17 5.2.3 optional and test parameters ....................... ................................................... .................................. 19 6 application information ............................ ................................................... ..................................... 21 6.1 matching network of the transmitter ................ ................................................... ................................. 21 6.2 reference crystal for the frequency synthesizer .... ................................................... .......................... 22 6.3 loop filter components ............................. ................................................... ........................................ 22 6.4 recommended modulation conditions .................. ................................................... ........................... 22 6.5 typical application schematics ..................... ................................................... .................... 23 7 packaging information.............................. ................................................... ..................................... 24
? semtech 2007 www.semtech.com 3 SX1223 the SX1223 is a single chip transmitter operating i n the 433, 868 and 915mhz license free ism (industr ial scientific and medical) frequency bands; the frequency range i s selectable between 425-475 mhz and 850-950 mhz. t he modulation scheme is 2-fsk. the circuit has 4 funct ional modes: sleep mode, where all the blocks are s witched off, standby mode, where only the crystal oscillator is on, synthesizer mode, where the frequency synthesiz er is running, and transmission mode, where all the blocks are on, including the power amplifier. it complies with eu ropean (etsi en 300-220-1) and north american (fcc part 15) regu lations. there are three different methods of modulation: - (mw1) pulling the vco in closed loop: all the spe cified bit rates can be implemented, but a dc-free coding scheme is needed (e.g. manchester), which means tha t the real information rate is half the bit rate, - (mw2) pulling the vco in open loop: all the speci fied bit rates can be implemented, and nrz coding i s allowed; but, since the control voltage of the vco will drift due to leakage currents, the duration of the transmission is limited, - (mw3) switching between two frequency divider rat ios in closed loop; bit rates from 1.2 to 19.2 kbit /s are achievable with this method. the circuit works on two selectable supply voltage ranges: - (sv1) the high range (2.2 v to 3.6 v), where the on-chip regulators are activated, - (sv2) the low range (2.0 v to 2.5 v), where the o n-chip regulators are off. a 3-wire bi-directional bus is used to communicate with SX1223 and gives access to the configuration r egister. an output clock of 1 mhz is user selectable for drivin g an external micro-controller. SX1223 comes in a rohs green tqfn-24 package (body size: 4 mm x 4 mm). 1 functional block diagram datain loop filter lock detect clock gen oscillator m crystal ldo ldo pa vco ? n,a pfd ? 2 mod open loop opamp vco ? n,a pfd ? 2 ? 2 ? 2 ldo bias data & control interface so si en sck dclk clkout vdd vddp rfout vddf xta xtb ld cpout varin vdd vddd SX1223 figure 1 : SX1223 block diagram
? semtech 2007 www.semtech.com 4 SX1223 2 pin description pin name i/o function 1 vdd - main analog power supply max 3.6v in sv1-mode max 2.5v in sv2-mode 2 vssp - pa ground 3 vddp - in sv1-mode: pa ldo output, capacitor needed in sv2-mode: pa power supply, max 2.5 v 4 rfout out rf output 5 vssp - pa ground 6 ptatbias/pac in/out ptat source bias resistor / p a start-up control capacitor 7 xtb in/out crystal oscillator pin & input for ext ernal reference 8 xta in/out crystal oscillator pin 9 vddd - in sv1-mode: digital ldo output, capacitor needed in sv2-mode: digital power supply, max 2.5v 10 vssd - digital ground 11 vdd - main digital power supply max 3.6v in sv1-mode max 2.5v in sv2-mode 12 ld out lock detect output 13 clkout out output clock (1 mhz) 14 dclk out data clock output 15 datain in data input 16 sck in 3-wire interface clock input 17 en in enable signal for the 3-wire interface 18 si in 3-wire interface data input 19 so out 3-wire interface data output 20 cpout out pll charge pump output 21 varin in vco varactor input 22 vssf - analog ground 23 vddf - in sv1-mode: analog ldo output, capacitor needed in sv2-mode: analog power supply max 2.5 v 24 cibias out ci source bias resistor note: thermal pad on the bottom of the package mu st be connected to ground. bottom view 1 24 thermal pad
? semtech 2007 www.semtech.com 5 SX1223 3 electrical characteristics 3.1 absolute maximum operating ranges stresses above the values listed below may cause pe rmanent device failure. exposure to absolute maximu m ratings for extended periods may affect device reli ability. symbol description min. max. unit vddmax supply voltage -0.4 3.9 v tmax storage temperature -55 125 c the device is esd sensitive and should be handled w ith precaution. 3.2 specifications 3.2.1 operating range symbol description min. max. unit vdd supply voltage (*) 2.0 3.6 v t temperature -40 85 c clop load capacitance on digital ports - 25 pf (*) divided in two ranges: - (sv1) high range, 2.2 v C 3.6 v, using on-chip r egulators, - (sv2) low range, 2.0 v C 2.5 v, without using th e regulators. 3.2.2 electrical specifications the table below gives the electrical specifications of the transmitter under the following conditions: supply voltage = 3.3 v, temperature = 25 c, 2-leve l fsk, fc = 915 mhz, output power = 10 dbm, bit rat e = 38.4 kb/s, d f = 100 khz, xtal = 16 mhz, modulation by pulling t he vco in open loop (mw2), and conditions as define d in section 6, unless otherwise specified. symbol description conditions min typ max unit iddsl supply current in sleep mode - 0.3 1 a iddst supply current in standby mode crystal oscillator running, clkout off - 0.2 0.3 ma iddfs supply current in fs mode frequency synthesiz er running - 5 6 ma iddt supply current during transmission 10 dbm 0dbm - - 25.8 14 - - ma ma fr frequency range 425 850 - - 475 950 mhz mhz fda frequency deviation for fr from 850 to 950 mhz 5 - 255 khz fda_l frequency deviation for fr from 425 to 475 mh z 5 - 200 khz d fda variation of frequency deviation - 15 - + 15 % br bit rate modulation modes mw1 mw2 1.2 - 153.6 kbit/s br_3 bit rate for mw3 mode modulation mode mw3 1.2 - 19.2 kbit/s spiclk spi clock frequency (sck) sck duty cycle 50% +/-10% 1 mhz
? semtech 2007 www.semtech.com 6 SX1223 symbol description conditions min typ max unit hrfop highest rf output power highest programmable output power 8 10 - dbm srfop rf output power steps rf output power step si ze (8 steps available) - 3 - db xtal crystal oscillator frequency recommended value : 16 mhz - - 40 mhz ts_os oscillator wake-up time from sleep mode - 0.8 2 ms ts_os_qs oscillator wake-up time in quick start-up mode quick start-up mode iddst_qs_typ=0.9ma (xco_quick_start, xco_high_i = 10) - 0.15 - ms ts_fs frequency synthesizer wake-up time from standby mode (oscillator running) frequency at most 5 khz away from the target - - 2 ms ts_tr transmitter wake-up time from fs mode (freque ncy synthesizer running) - - 500 s td_tx transmission duration in mw2 mode duration during which the output signal is a proper fsk signal and the carrier frequency doesnt drift by more than 50 khz from the time when the transmitter has reached its steady-state (including pa) 30 - - ms td_txw transmission duration in mw2 mode same conditions as td_tx, but over the whole temperature range 15 - - ms acp power transmitted in the 150 khz adjacent channel at 10 dbm output power, modulated signal measured on a 150 khz bandwidth centered at 150 khz from the carrier, d f = 40 khz - -16 dbm acp_mw3 power transmitted in the 250 khz adjacent channel in mw3 modulation mode at 10 dbm output power, modulated signal measured on a 250 khz bandwidth centered at 250 khz from the carrier, d f = 60 khz - -23 -17 dbm phn phase noise of the output signal at 10 dbm output power, unmodulated signal measured at 50 khz from the carrier in mw3 mode - -83 -80 dbc/hz clkout output clock on pin clkout - 1 - mhz vih digital input level high % vdd 75 - - % vil digital input level low % vdd - - 25 %
? semtech 2007 www.semtech.com 7 SX1223 4 general description the SX1223 is a 2-level fsk transmitter. the circui t operates in one of two frequency ranges, 425 to 4 75 mhz, and 850 to 950 mhz, allowing the 3 main ism frequency b ands (434 mhz, 869 mhz and 915 mhz) to be addressed by the circuit. it is capable of operating at data rat es between 1.2 and 153.6 kbit/s, making it ideally suited for applications where high data rates are required. the SX1223 is a highly programmable device C channe l, bit rate, frequency deviation and output power C which makes it extremely flexible to meet a large number of end user requirements. the main functional blocks of the SX1223 are the fr equency synthesizer, the modulator, the power ampli fier (pa), the voltage regulators and some additional service blocks. the device also includes a set of configura tion registers and a digital interface. in a typical application, the SX1223 is programmed by a microcontroller via t he 3-wire serial bus si, so, sck to write to and read from the inter nal registers. the frequency synthesizer generates the carrier (the local oscillator (lo) s ignal). the modulator performs the modulation of the carrier by the input bit stream. the power amplifier amplifies the modulated rf signal to the antenna p ort. the voltage regulators generate regulated supply voltages for the differe nt parts of the chip, and allow battery voltages up to 3.6 v to be used. the service blocks provide the internal voltage and current sources a nd provide all the necessary functions for the circuit to work properly. the configuration registers are a set of registers that are used to store vari ous settings to operate the SX1223 transmitter circuit. please refer to section 5.2 fo r the detailed descriptions of these registers. the se registers are accessed in write or read mode through the 3-wire s erial bus, as described in section 5.1. the digital interface provides internal control signals for the whole ci rcuit according to the configuration register settings. 4.1 frequency synthesizer 4.1.1 general structure the frequency synthesizer is an integer-n pll and c onsists of a voltage-controlled oscillator (vco), a crystal oscillator, a prescaler, programmable frequency div iders and a phase-detector. the loop-filter is exte rnal for flexibility and can be a simple passive circuit. th e lengths of the m and n and a counters are respect ively 12, 12 and 6 bits. to enable the prescaler prescal_s register (address 16, bit 4) has to be written to 1. the m, n and a values can be calculated from the formula: ) 16( ) 2( a n freqband m f f xco rf + - = where f xco : crystal oscillator frequency f rf : rf frequency freqband: 0: rf frequency 425-475 mhz 1: rf frequency 850-950 mhz m is the divide factor applied to the reference fre quency, n and a are the counters of the frequency d ivider in the feedback loop of the pll. there are two sets of each of these divide factors (m0, n0, a0 and m1, n1, a1). in modulation modes mw 1 and mw2 (register bit modulation1=0), only the m0, n0 a nd a0 are used to fix the carrier frequency. if mod ulation by using the dividers is selected (mw3, modulation1=1, modulation0=0), the two sets are used to program t he two rf
? semtech 2007 www.semtech.com 8 SX1223 frequencies corresponding to the transmission of th e two possible values 0 and 1; these frequencie s are then separated by twice the specified single sided frequ ency deviation d f. 4.1.2 crystal oscillator the crystal oscillator (xco) provides the pll with the reference signal. the schematic of the crystal oscillator's external components for 16 mhz is shown in figure 2 . 5p6 5p6 xtb, pin 7 xta, pin 8 figure 2 : external crystal oscillator circuit with additional (optional) external capacitances the crystal should be connected between pins xta an d xtb (pin 8 and 7). either internal or external lo ading capacitors for the crystal can be used. internal ca pacitors can be enabled by setting the xcocap_en bi t to 1. faster start-up time is expected when using external capac itors. the total capacitance when xcocap_en=1 (and no external capacitors) is 9 pf. using a crystal with a load capacitance of 9 pf will give the expected o scillation frequency. if xcocap_en=0, the loading capacitors can be calcu lated by the following formula: parasitic l c c c c + + = 2 1 1 1 1 the parasitic capacitance is the pin input capacita nce and pcb stray capacitance. for instance, for a 9pf load crystal and a total parasitic capacitance of 6 pf t he recommended values of the external load capacito rs are 5.6 pf. if an external reference is going to be used instea d of a crystal, the signal shall be applied to pin 7, xtb. due to internal biasing, ac coupling is recommended for us e between the external reference and the xtb pin. the start-up time of the crystal oscillator can var y from 150us to 800us depending on the settings sho wn in table 15. therefore, to save current consumption, the xco should be turned on before any other circuit block . during start-up the xco amplitude will eventually reach a sufficient level to trigger the m-counter. after co unting 2 m- counter output pulses the rest of the circuit is en abled. two bits are available to speed up the crystal osci llator start-up: xco_high_i increases the bias curr ent and xco_quick_start boosts this current but only at the start; the first output pulse from the m-divider t urns this boost current off. typical values for xco start-up time and current consumption are tablulated below: xco_quick_start, xco_high_i 00 01 10 11 iddst [ua] 200 250 900 950 ts_os [us] 800 750 200 150 table 1 : oscillator start-up time a reference clock can be generated by SX1223 for us e by an external microcontroller. the clkout_en con figuration bit determines the status of the clkout pin. when s et high clkout is enabled, otherwise its disabled. when enabled, the output frequency at clkout is the crys tal oscillator frequency divided by 16, and is then 1 mhz for a crystal at 16 mhz. this clock signal is disabled in sleep mode. when disabled, the clkout pin is set t o ground. 4.1.3 vco the vco is fully integrated and has no external com ponents. it oscillates at 1.8 ghz and is divided by 2 or 4 in the 900 mhz or the 450 mhz band respectively (freqband = 1 or 0). additionally two bits in the configurati on registers set the vco frequency and three bits control the bi as current. the two vco_freq bits have to be progra mmed by
? semtech 2007 www.semtech.com 9 SX1223 the user according to the selected frequency band, whereas the three vco_ib bits can be either forced by the user or set automatically by the circuit which will sele ct the combination having the best phase noise. thi s automatic setting can be enabled by setting the three vco_ib bits to 0. table 2 lists the bias setting used for the differe nt vco_freq settings in automatic mode. when any of the vco_ib bit is set to 1, it will overrule the automatic set ting. rf frequency vco_ib2 vco_ib1 vco_ib0 vco_freq1 vco_freq0 425/850 mhz 1 1 1 0 0 434/868 mhz 1 0 1 0 1 457/915 mhz 0 1 1 1 0 475/950 mhz 0 0 0 1 1 table 2 : vco bit settings. the bias bits optimize the phase noise, and the fre quency bits control a capacitor bank in the vco. th e tuning range, the rf frequency versus varactor voltage, is dependent on the vco frequency setting, and is sho wn in figure 3. when the tuning voltage is in the range f rom 1 to 1.6v, the vco gain is at its maximum, appr oximately 65- 70 mhz/v. it is then recommended that the varactor voltage is kept as much as possible in this range. figure 3 : rf frequency vs. varactor voltage and vco frequency bit the input capacitance at the varactor pin must be t aken into considerations when designing the pll loo p filter. this can be critical when designing a loop filter with h igh bandwidth, which gives relatively small compone nt values. the input capacitance is approximately 6 pf. for test purposes, the vco can be bypassed by apply ing a differential local oscillator (lo) signal to the device on pin cpout and varin. a resistor of 18 k to ground and a series capacitor of 47 pf are need ed on both pins for proper biasing. the register bit vco_by must be set to 1. vco gain vdd=3.3v, ldo_en=1, vco_ib=0 800 820 840 860 880 900 920 940 960 980 1000 1020 1040 0 0.5 1 1.5 2 2.5 vvaractor [v] freq [mhz] vco_freq=11 vco_freq=10 vco_freq=01 vco_freq=00
? semtech 2007 www.semtech.com 10 SX1223 4.1.4 charge pump the charge pump current can be set to either 125 or 500 m a by the cp_hi bit. the default value at power-up i s 125 m a (cp_hi = 0). the choice of this current affects the loop filter component values (see section 4.1. 5). for most applications the lowest current mode is recommende d. for those applications using a high phase detect or frequency and a high pll bandwidth, 500 m a may provide a better solution. 4.1.5 loop filter the design of the pll filter will strongly affect t he performance of the frequency synthesizer. the pl l filter is kept external for flexibility. the parameters to be cons idered when designing the loop filter for the sx122 3 are primarily the modulation mode and bit rate. these will also a ffect the switching time and phase noise. the frequency modulation can be done in three diffe rent ways with the SX1223, either by closed-, open loop vco modulation or by modulation with the internal divid ers, see table 3 and modulation selection guide in table 35. modulation1 modulation0 state comments 0 0 closed loop vco-modulation (mw1) vco is phase-locked 0 1 open loop vco-modulation (mw2) vco is free-running 1 0 modulation by a,m and n (mw3) modulation inside pll 1 1 not used table 3 : modulation modes vco ? m ? n,a pfd xco ? 2 mod 20 21 r1 c2 c3 SX1223 pcb vco ? m ? n,a pfd xco ? 2 mod 20 21 r1 SX1223 pcb vco ? m ? n,a pfd xco ? 2 mod 20 21 r1 c 2 c3 SX1223 pcb ol opamp c1 vco ? m ? n,a pfd xco ? 2 mod 20 21 r1 c3 SX1223 pcb ol opamp vco ? m ? n,a pfd xco ? 2 mod 20 21 r1 c2 c3 SX1223 pcb r2 c1 vco ? m ? n,a pfd xco ? 2 mod 20 21 r1 c3 SX1223 pcb r2 modulation mw1 modulation mw2 modulation mw3 figure 4 : modulation modes in closed loop vco modulation (mw1), the pll bandwi dth needs to be sufficiently low ( bit rate / 20), so as to prevent the vco tracking the modulation and cancell ing the modulation. using the dividers in mw3 mode, the pll needs to lo ck on a new carrier frequency for every new data bi t. now the pll bandwidth needs to be sufficiently high ( bit rate / 2). it may be necessary to implement a third order filter to futher suppress the phase detector frequency spurs, for the open loop vco modulation case (mw2), the pl l bandwidth can be large, as the pll is deactivated during the transmission burst and there is no requirement to supress the phase detector frequency to increase the transmission time in the open loop case, a capacitor of 47 nf can be connected on pin varin to ground (npo type is advised if the transmission dur ation is critical). the internal opamp must be enab led to drive this capacitor, by setting the bit ol_opamp_en to 1 . a schematic for a third order loop filter is shown in figure 5a. for a second order filter, c3 is not connected and r2 is set to 0 w . when designing a third order loop filter, the int ernal capacitance on the varin pin of approximately 6 pf must be taken into consideration. figure 5b show s the loop filter configuration for the open loop v co modulation case.
? semtech 2007 www.semtech.com 11 SX1223 c3 c1 cpout, pin 20 c2 r1 r2 varin, pin 21 c1 cpout, pin 20 c2 r1 varin, pin 21 c3 47nf a) b) figure 5 : loop filter for a) closed loop modulation and b) open loop modulation 4.1.6 lock detect a lock detector can be enabled by setting ld_en=1. when enabled pin ld is set high, indicating that th e pll is in lock. the lock detect signal can also be used to co ntrol the pa; if ld is low the pa is turned off and vice versa. to enable this function, the pa_ldc_en must be set to 1 (see section 4.3). care must be taken when monitoring the ld during da ta transmission using the closed loop modulation. t he ld may show that the pll is not locked, especially whe n the loop filter bandwidth is too high relative to the bit rate. 4.2 modulator 4.2.1 introduction the modulator has a high degree of flexibility, and there are thus several values that need programmin g. first, the settings concerning the data bit rate must be deter mined, then these values will be used in the calcul ation of the frequency deviation. finally the user must check th at the modulator wont saturate with the values cho sen. 4.2.2 data interface the "data interface" can be programmed to synchrono us or asynchronous mode (see table 4). sync_en state comments 0 dataclk pin off transparent transmission of data 1 dataclk pin on. bit-clock is generated by transm itter table 4 : synchronizer mode in asynchronous mode only the datain pin is used fo r transmitting the data to the SX1223. in synchronous mode the SX1223 is defined as "maste r" and provides a data clock on pin dclk that allow s the user to utilize low cost micro controller reference frequency. the data interface is defined in such a way that all user actions should take place on falling edges of dclk as illustrated in figure 6. the data are sampled by the SX1223 on the rising edges of dclk. datain dclk figure 6: time diagram of the data interface in synchronous mode before entering into transmit mode (mw1 or mw2), it is important to set datain to high impedance. the data is provided directly to the modulation circuit and vio lation of this may cause abnormal behavior.
? semtech 2007 www.semtech.com 12 SX1223 4.2.3 bit rate setting for mw1 and mw2 the bit rate is set by first dividing the crystal o scillator frequency by an integer in the range [1.. 63] in a programmable divider, then this frequency is divide d further by powers of two. the equation describing the bit rate as a function of refclk_k and brn is brn xtal k fclk f br + = 3 2 _ re (4.1) where: f xtal : crystal oscillator frequency. refclk_k: integer in the range [1..63] (6 bit). brn : integer in the range [0..5] (3 bit). a procedure to determine the settings for the desi red bit rate is described below: 1. set brn to 0. 2. calculate refclk_k by using this formula: brn xtal br f k fclk + = 3 2 _ re . 3. if refclk_k is too high, increment n by one, and repeat step 2, above in some cases several combinations of refclk_k and brn will provide the required bit rate. in these cases brn should be chosen with the following in mind: a lowe r brn offers better waveform shaping or spectral efficie ncy, but may cause modulator saturation at some bit rates. 4.2.4 deviation setting for mw1 and mw2 frequency deviation is controlled by user parameter s refclk_k , mod_i , and mod_a together with physical parameters f xtal and k vco . all user parameters can be set in software, and f xtal (crystal oscillator frequency) is set when designing in the radio chip. k vco (vco gain) is a parameter of the radio chip, and i s not controllable by the user. the crystal oscillator frequency, f xtal , is divided by refclk_k to generate the modulator clock. since this modula tor clock is controlling the rise and fall times for th e modulator, the frequency deviation is inversely p roportional to this clock. the relationship is shown in equation (4.2). xtal dev f k fclk f _ re (4.2) it is assumed that k will be constant for most applications to keep bit -rate and shaping constant, although this is not a requirement. the control parameters of the frequency deviation a re mod_i and mod_a . of these two, mod_i is the parameter that controls the signal generation, while mod_a controls attenuation of this signal. the reason fo r using an attenuator is to be able to generate small deviatio ns at high values of refclk_k . the relationship is shown in equation (4.3). a mod dev i mod f _ 2 _ (4.3) finally, the vco gain is given by equation (4.4). ( ) ( ) freqband freqband f const const k c vco - - + = 2 2 2 1 (4.4) where: const 1 : 9 10 6324 . 30 - const 2 : 7. 54 f c : carrier frequency. freqband : frequency band. 0: 400mhz and 1: 900mhz.
? semtech 2007 www.semtech.com 13 SX1223 from equation (4.4), it can be seen that vco is pro portional to carrier frequency. mod_i is the best p arameter to alter to counteract this effect if necessary. combining equations (4.2), (4.3), and (4.4) gives a n expression for the frequency deviation: ( ) ( ) freqband freqband f const const i mod f f c a mod xtal - - + = d 2 2 2 _ refclk_k 2 1 _ (4.5) 4.2.5 shaping for mw1 and mw2 the modulation waveform will be shaped due to the c harging and discharging of a capacitor. the wavefor m looks like a gaussian filtered signal with a bandwidth period-product (bt) given by: brn bt 2 = (4.6) it can be seen from this equation that a low brn gives a low shaping factor. in addition to this, it is possible to smooth the m odulator output in a programmable low-pass filter. this filter is controlled by the parameter mod_f . the parameter should be set according to equation (4.7). br f mod 3 10 150 _ (4.7) 4.2.6 modulator saturation for mw1 and mw2 the modulator output voltage is generated with a ca pacitor that is being charged. this means that ther e is a risk of saturating the modulator if the charge received by the capacitor is too large. the maximum value of mod_i can be determined by using equation (4.8). 1 10 28 _ re _ 6 + ? ?? ? ? ?? ? - k fclk f i mod xtal (4.8) if it turns out that the mod_i -range is too small for the application, the soluti on can be found by increasing brn and decreasing refclk_k accordingly. 4.2.7 summary of modulator settings for mw1 and mw2 the necessary equations needed for the use of the m odulator are (4.1), (4.5), (4.6), (4.7), and (4.8). the table below gives a summary of the meaning of the paramet ers. symbol range (inclusive) explanation refclk_k 1..63 the crystal oscillator frequency is divided by this number to produce the modulator clock, and it is divided further down by 8 to produ ce bit rate clock. brn 0..5 number of extra divide-by-two for the bit rate clock. mod_f 0..3 programmable smoothing filter after atte nuator. this can be programmed in four steps, and will produce reasonable results for the highest bit rates. mod_i 1..31 frequency deviation. the deviation is l inearly dependent on this variable. mod_a 0..4 frequency deviation attenuator (or range selector). the attenuations are (values 0 through 4, respectively) 1 1 , 2 1 , 4 1 , 8 1 , and 16 1 . table 5: modulator settings 4.2.8 frequency deviation setting for mw3 in mw3 the modulation is done by switching between two frequency divider ratio sets: m 0 , n 0 , a 0 and m 1 , n 1 , a 1 . the frequency f 0 will be generated using the first set and frequenc y f 1 using the second set, corresponding to the transmission of the two possible values 0 and 1 .
? semtech 2007 www.semtech.com 14 SX1223 the single sided frequency deviation d f is half of the difference between f 0 and f 1 . bit rates from 1.2 to 19.2 kbit/s are achievable with this method. 4.3 power amplifier the output power of the pa is programmable in 8 ste ps, with approximately 3 db between each step. this is controlled by bits pa2 to pa0 according to table 6 below. pa2..pa0 = 111 provides the maximum output power of typically 10 dbm. pa2 pa1 pa0 output power 0 0 0 21db attenuation 0 0 1 18db attenuation 0 1 0 15db attenuation 0 1 1 12db attenuation 1 0 0 9db attenuation 1 0 1 6db attenuation 1 1 0 3db attenuation 1 1 1 maximum power table 6 : pa power settings the pa is normally controlled by the two mode bits (off for all cases other than mode1, mode0 = 11). the pa can in addition be controlled by the lock detector, if the bit paldc_en is set high (and ld_en=1). in th is case, once ld goes high after entering the transmit mode, the pa is turned on and will remain on until a new event c hanging the working mode occurs (such as a new configuration tr ansmitted through the 3-wire interface). during open loop vco modulation, mw2, the pll is de activated during the transmission time. after an op en loop transmission, the frequency may have drifted off, a nd it is therefore important that the pa is turned off before the pll is activated. the pa behaves this way as long a s paldc_en=1. after a transmission burst, datain mu st be set to high impedance, the pa is turned off and the pll is reactivated. once ld goes high again, the p a is turned on and a new burst of data can be transmitted. to reduce the harmonics for passing the etsi and fc c regulations a 3 rd order lc-filter (t or p configuration) should be implemented between the output of the pa and the antenna port. the ramp-up of the pa is achieved using an internal capacitor (approx. 29pf). if this is not sufficien t to pass relevant regulations, bit pac_en can be enabled and an external capacitor connected to pin 6. using pa_ib3,2 and pab_ib3,2 bits the reference cur rent can be selected to bias the pa and the pa buff er as shown in table 31. an 82k resistor should be connected between pin 24 and gr ound for the ci bias. if the option ptat bias sourc e with external resistor is chosen, an 18k resistor should be connected between pin 6 and gro und. this option can not be used when pac_en option is s elected. in this case the resistor is replaced by a capacitor, and the functionality changes as described above. 4.4 voltage regulators the SX1223 has three internal low dropout regulator s (ldos) powering up different parts of the circuit , as can be seen from the block diagram (figure 1). the ldos ca n be turned off (default setting is on) by setting the ldo_en=0. when ldo_en=1, the power supply range is 2.2 - 3. 6 v (sv1). power must be applied to pins 1 and 11. a good quality factor capacitor is needed on each of the l do output for stability (pins 3, 9 and 23). in slee p mode all the ldos are turned off. the interface and control bloc ks run on unregulated power, and the register conte nts will be stored and hence the device can be programmed whils t in this mode. when ldo_en=0, the power supply range is 2.0 - 2.5 v (sv2). power must be applied to pin 1, 3, 9, 11 a nd 23. in this case capacitors are only needed for normal noi se decoupling.
? semtech 2007 www.semtech.com 15 SX1223 5 serial interface definition and principles of ope ration 5.1 serial control interface a 3-wire bi-directional bus (sck, si, so) is used t o communicate with SX1223 and gives access to the configuration register. sck and si are input signal s supplied externally, for example by the microcont roller. the SX1223 configures the so signal as an output pin du ring read operation, and it is tri-stated in other modes. the falling edge of the sck signal is used to sample th e si pin to write data into the internal shift regi ster of the SX1223. the rising edge of the sck signal is used to output data by the SX1223 to the so pin, so the microcont roller should sample data at the falling edge of sck. be aware t hat reading data on so output is forbidden whilst i n transmit mode. the signal en must be low during the whole write an d read sequences. in write mode the actual content of the configuration register is updated at the rising edg e of the en signal. before this, the new data is st ored in temporary registers whose content does not affect the transce iver settings. the timing diagram of a write sequence is given in figure 7 below. the sequence is initiated when a st art condition is detected, that is when the si signal is set to 0 during a period of sck. the next bit is a read/w rite (r/w) bit which should be 0 to indicate a write operation. the next 5 bits are the address of the control regi ster a[4:0] to be accessed, msb first. then, the next 8 bits are the data to be written in the register. the data on si should change at the rising edges of sck, and is sampled at the fall ing edge of sck. the si line should be at 1 for a t least one clock cycle on sck before a new write or read seque nce can start. in doing this, users can do multiple registers write without a rising en signal in between. the du ty cycle of sck must be between 40% and 60% and the maximum frequency of this signal is 1 mhz. over the operating supply and temperature range, set-up and hold time for si on the falling edge of sck are 200ns. a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 sck si enso hz figure 7: write sequence into configuration registe r the time diagram of a read sequence is given in fig ure below. the sequence is initiated when a start c ondition is detected, that is when the si signal is set to 0 during a period of sck. the next bit is a read/writ e (r/w) bit which should be 1 to indicate a read operation. the nex t 5 bits are the address of the control register a[ 4:0] to be accessed, msb first. then the data from the registe r are transmitted on the so pin. the data become va lid at the rising edges of sck and should be sampled at the fa lling edge of sck. after this, the data transfer is terminated. the si line must stay high for at least one clock c ycle on sck to start a new write or read sequence. the typical current drive on so is 2ma @ 2.7v, the maximum load is clop. when the serial interface is not used for read or w rite operations, both sck and si should be set to 1. except in read mode, so is set to hz.
? semtech 2007 www.semtech.com 16 SX1223 figure 8: read sequence of configuration register. 5.2 configuration and status registers the SX1223 has several operating modes and configur ation parameters which can be programmed by the use r. these modes and parameters are stored in a set of i nternal configuration registers that can be accesse d by the microcontroller through the 3-wire serial interface . the detailed contents of the configuration register s are given in the next table. the value attached t o each parameter is the default value at power-up. all the undefined bits in the table below should be kept t o 0. address default value data a[6:0] d[7:0] hex d7 d6 d5 d4 d3 d2 d1 d0 0000000 0x3f - mode [1:0] pa [2:0] clkout_en sync_en 0000001 0x7d modulation [1:0] freq_band xcocap_en ldo_en ol_opamp_ en pa_ldc_en ld_en 0000010 0x02 - - pac_en xco_quick_ start xco_high_ current cp_hi vco_freq [1:0] 0000011 0x4b mod_i [4:0] mod_a [2:0] 0000100 0x0c - - brn [2:0] mod_f [2:0] 0000101 0x1a - - refclk_k [5:0] 0000110 0x02 - - a0 [5:0] 0000111 0x00 - - - - n0 [11.8] 0001000 0x76 n0 [7:0] 0001001 0x00 - - - - m0 [11:8] 0001010 0x22 m0 [7:0] 0001011 0x02 - - a1 [5:0] 0001100 0x00 - - - - n1 [11:8] 0001101 0x76 n1 [7:0] 0001110 0x00 - - - - m1 [11:8] 0001111 0x22 m1 [7:0] 0010000 0x20 vco_ib [2:0] prescal_s vco_by - - - 0010001 0xdd pa_ib [3:0] pab_ib [3:0] table 7 : contents of the configuration registers and their v alues at power-on 5.2.1 operating modes the SX1223 can be programmed into four different mo des by the mode1 and mode0 bits, as illustrated in table 8. add bits mode1 mode0 mode description 0 0 sleep mode all blocks off, register configurati on kept (default) 0 1 standby mode crystal oscillator enabled 1 0 synthesizer mode crystal oscillator, frequency synthesizer enabled 0 6-5 1 1 transmit mode crystal oscillator, frequency syn thesizer, pa enabled table 8: SX1223 operating modes
? semtech 2007 www.semtech.com 17 SX1223 5.2.2 other settings the tables below give the definition of all the par ameters of the configuration registers besides the working modes. add bits pa2 pa1 pa0 state 0 0 0 21db attenuation 0 0 1 18db attenuation 0 1 0 15db attenuation 0 1 1 12db attenuation 1 0 0 9db attenuation 1 0 1 6db attenuation 1 1 0 3db attenuation 0 4-2 1 1 1 max output (default) table 9: power amplifier output power add bit clkout_en state comments 0 clkout off output is 0 volt on pin clkout. 0 1 1 clkout on a clock at xco frequency divided by 16 is available on pin clkout. (default) table 10: output clock add bit sync_en state comments 0 dclk pin off transparent transmission of data 0 0 1 dclk pin on bit- clock is generated by transceiver (default) table 11: synchronizer mode add bit modulation1 modulation0 state comments 0 0 closed loop vco-modulation (mw1) vco is phase-locked 0 1 open loop vco-modulation (mw2) vco is free- running (default) 1 0 modulation by m, n and a (mw3) modulation inside pll 1 7-6 1 1 not used table 12: modulation mode add bit freqband comments 0 rf frequency 425-475 mhz 1 5 1 rf frequency 850-950 mhz (default) table 13: frequency band add bit xcocap_en comments 0 internal capacitors for the crystal oscillator tu rned off 1 4 1 internal capacitors for the crystal oscillator turn ed on, external capacitors not needed (default) table 14: xco internal capacitor
? semtech 2007 www.semtech.com 18 SX1223 add bit xco_quick_start xco_high_current comments 0 0 normal xco bias current (default) 0 1 higher xco bias current 1 0 quick start of xco with normal bias current in st eady state 2 4-3 1 1 quick start of xco with higher bias current in st eady state table 15: xco start-up control add bit ldo_en comments 0 ldo turned off, min/max vdd is 2.0/2.5 v 1 3 1 ldo turned on, min/max vdd is 2.2/3.6 v (default) table 16: low dropout voltage regulator on/off add bit ol_opamp_en state comments 0 open loop opamp off 1 2 1 open loop opamp on (default) when opamp is enabled, a capacitor can be added to the varactor pin that will increase the transmission time in open loop modulation (mw2) table 17: open loop opamp on/off add bit pa_c comments 0 startup time of pa controlled by internal capacitor ; ptat source using the resistor connected to pin6 can be used (default) 2 5 1 startup time of pa controlled by external capacitor connected to pin 6; ptat source using the resistor connected to pin6 is not available table 18: pa start-up control add bit paldc_en comments 0 pa is only controlled by mode1 and mode0: pa on in transmit mode (mode1=mode0=1) (default) 1 1 1 in transmit mode, pa is turned on/off by lock det ect (i.e. ld=1 -> pa on) table 19: lock detect controlled pa add bit ld_en state comments 0 ld off output is low 1 0 1 ld on a high indicate a pll lock (default) table 20: lock detector add bit cp_hi comments 0 pll charge pump current is 125 a (default) 2 2 1 pll charge pump current is 500 a table 21: charge pump current add bits vco_freq1 vco_freq0 comments (*) 0 0 setting for 850 mhz 0 1 setting for 868 mhz 1 0 setting for 915 mhz (default) 2 1-0 1 1 setting for 950 mhz (*) assuming freqband=1. when freqband=0, the rf fr equency is halved. table 22: vco frequency
? semtech 2007 www.semtech.com 19 SX1223 add bits mod_i comments 1..31 the deviation frequency is linearly dependent of mod_i 3 7-3 table 23: modulator current setting for frequency d eviation add bits mod_a comments 3 2-0 0..4 frequency deviation attenuator (or range selector). the attenuations are (values 0 through 4, respectively) 1 1 , 2 1 , 4 1 , 8 1 , and 16 1 . table 24: modulator attenuator setting for frequenc y deviation add bits brn comments 4 5-3 0..5 the bit rate clock is set by dividing the crystal o scillator frequency by refclk_k*2^(3+brn) table 25: bit rate setting add bits mod_f comments 4 2-0 0..3 programmable smoothing filter after attenuator. thi s can be programmed in four steps, and will produce reasonable results for the highest bit rates. table 26: modulator filter setting add bits refclk_k comments 5 5-0 1..63 the crystal oscillator is divided by this number to produce modulator clock and it is divided further down by 2^(3+brn) to produce the bit rate clock. table 27: modulator and bit rate clock setting add bit prescal_s state comments 0 (default) reserved. 16 4 1 prescaler enabled ) 16( ) 2( a n freqband m f f xco rf + - = table 28: prescaler enable bit 1 should be written in prescal_s register to oper ate SX1223 pll dividers. 5.2.3 optional and test parameters in most applications, the user has only to be conce rned with the parameters given in sections 5.2.1 an d 5.2.2. however some options and test modes are available f or special purposes. they are described in the tabl es below. add bits vco_ib2 vco_ib1 vco_ib0 comments - default = [0 0 1] 1 1 1 bias setting for 850 mhz 1 0 1 bias setting for 868 mhz 0 1 1 bias setting for 915 mhz 16 7-5 0 0 0 bias setting for 950 mhz table 29: vco bias the two vco_freq bits have to be programmed by the user according to the selected frequency band, wher eas the three vco_ib bits can be either forced by the user or set automatically by the circuit which will sele ct the combination having the best phase noise. this autom atic setting can be enabled by setting the three vc o_ib bits to 0.
? semtech 2007 www.semtech.com 20 SX1223 add bit vco_by state comment 0 vco is active (default) 16 3 1 vco is bypassed when vco is bypassed, a differential signal can be applied to the circuit using pin cpout and varin table 30: vco bypass bit add bits pa_ib3 pa_ib2 state 0 0 pa uses bias current from ptat bias source, externa l resistor (pin 6) 0 1 pa uses bias current from ci bias source, external resistor (pin 24) 1 0 pa uses bias current from internal bias source, pta t 17 7-6 1 1 pa uses bias current from internal bias source, pta t + ci (default) add bits pa_ib1 pa_ib0 state 0 0 pa bias current setting, lowest bias current 0 1 pa bias current setting (default) 1 0 pa bias current setting 17 5-4 1 1 pa bias current setting, highest bias current add bits pab_ib3 pab_ib2 state 0 0 pabuffer uses bias current from ptat bias source, e xternal resistor (pin 6) 0 1 pabuffer uses bias current from ci bias source, ext ernal resistor (pin 24) 1 0 pabuffer uses bias current from internal bias sourc e, ptat 17 3-2 1 1 pabuffer uses bias current from internal bias sourc e, ptat + ci (default) add bits pab_ib1 pab_ib0 state 0 0 pabuffer bias current setting, lowest bias current 0 1 pabuffer bias current setting (default) 1 0 pabuffer bias current setting 17 1-0 1 1 pabuffer bias current setting, highest bias current table 31: pa and pabuffer bias current setting
? semtech 2007 www.semtech.com 21 SX1223 6 application information this section provides details of the recommended co mponents values for the frequency dependant blocks of the SX1223. note that these values are dependent upon c ircuit layout and pcb structure. 6.1 matching network of the transmitter the optimum load impedances for 10 dbm output power at the three main frequencies are given in the fol lowing table. 434 mhz 869 mhz 915 mhz pa optimum load 19.4-j2.6 23.5-j1 23.5+j8 table 32: optimum load impedances for 10 dbm output power the schematic of the recommended matching network a t the output of the transmitter is given in figure 9 on the next page. figure 9: transmitter output network the p -section is used to provide harmonic filtering in o rder to satisfy fcc and etsi regulations. the typical component values of this matching circu it are given below. name typical value for 434 mhz typical value for 869 mhz typical value for 915 mhz tolerance ct1 6.8pf 6.8 pf 6.8 pf 5% ct2 1pf nc nc 5% ct3 10pf 15 pf 33 pf 5% ct4 10pf 6.8 pf 4.7 pf 5% lt1 22nh 4.7 nh 4.7 nh 5% table 33: typical component values for the recommen ded matching network at the output of the transmitt er c t4 c t2 lt1 c t1 SX1223 c t3
? semtech 2007 www.semtech.com 22 SX1223 6.2 reference crystal for the frequency synthesizer the crystal for the reference oscillator of the fre quency synthesizer should have the following typica l characteristics: name description min. value typ. value max. value fs nominal frequency - 16.0 mhz (fundamental) - cl load capacitance for fs (on-chip) - 9 pf - rm motional resistance - - 40 w cm motional capacitance - - 30 ff c0 shunt capacitance - - 7 pf table 34: crystal characteristics 6.3 loop filter components the loop filter component values used in mw2 mode for specification validation are presented below; ( see fig.5b) r1 c1 c2 c3 12k 470pf 4.7nf 33nf 6.4 recommended modulation conditions bit rate [kb/s] frequency deviation [khz] modulation type max. carrier frequency step coding allowed transmission mode 1.2 5 to 255 2.4 5 to 255 4.8 5 to 255 9.6 10 to 255 19.2 20 to 255 mw3 up to 300 khz, not regularly spaced nrz continuous 40 to 255 mw1 100 khz manchester continuous 32.8 100 to 255 mw2 100 khz nrz burst (1 kbits for d f 100 khz) 40 to 255 mw1 100 khz manchester continuous 38.4 100 to 255 mw2 100 khz nrz burst (1 kbits for d f 100 khz) 80 to 255 mw1 100 khz manchester continuous 76.8 100 to 255 mw2 100 khz nrz burst (2 kbits for d f 100 khz) 200 to 255 mw1 100 khz manchester continuous 153.6 100 to 255 mw2 100 khz nrz burst (4 kbits for d f 100 khz) table 35: modulation type selection
? semtech 2007 www.semtech.com 23 SX1223 6.5 typical application schematics vdd c10 c11 slave in /select spi serial clock tx data input tx data clock clock output slave out pll lock detect SX1223 tqfn24 4x4 1 2 3 4 5 6 18 17 16 15 14 13 7 8 9 10 11 12 24 23 22 21 20 19 vdd vssp vddp rfout vssp ptat/pac xtb xta vddd vssd vdd ld si /en sck datain dclk clkout cibias vddf vssf varin cpout so c1 l1 vdd vdd nc c2 c3 c4 c5 c6 c7 c8 c9 r1 r2 figure 10: application schematics note: refer to chapter 4.3 for pin 6. please contact semtech for applications schematics and bills of materials for reference designs.
? semtech 2007 www.semtech.com 24 SX1223 7 packaging information SX1223 comes in a 24-pin rohs green tqfn 4x4 packag e as shown in figure 11 below. figure 11 : package dimensions the exposed die pad on the bottom of the chip shoul d be soldered. please contact semtech for foot prin t recommendations and pcb gerber files of semtech ref erence designs.
? semtech 2007 www.semtech.com 25 SX1223 contact information ? semtech 2006 all rights reserved. reproduction in whole or in pa rt is prohibited without the prior written consent of the copyright owner. the information presented in this document does not for m part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability wil l be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual propert y rights. semtech assumes no responsibility or liability whatsoever for any fail ure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, ex posure to parameters bey ond the specified maximum ratings or operation outside the specified range. semtech products are not designed, intended, author ized or warranted to be suitable for use in life-support applications, devices or systems or ot her critical applications. inclusion of semtech products in such applications is understood to be u ndertaken solely at the customers own risk. should a customer purchase or use semtech products for any such unauthorized application, the customer shall indemnify and hold semtech and its officers, employees, subsidiar ies, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. semtech corporation wireless and sensing products division 200 flynn road, camarillo, ca 93012 phone (805) 498-2111 fax : (805) 498-3804

▲Up To Search▲

Price & Availability of SX1223

	To Download SX1223 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .